1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to a process for fabricating a stacked etch, contactless EPROM array that utilizes cross-point cells and internal access transistors.
2. Discussion of the Prior Art
An electrically programmable read only memory (EPROM) device as a non-volatile memory integrated circuit which is used to store binary data. Power can be removed from an EPROM without loss of data. That is, upon reapplying power, the originally stored binary data is retained.
In addition to its data retention capability, an EPROM can also be programmed to store new binary data. Reprogramming is accomplished by first exposing the EPROM to an ultra-violet (UV) light source in order to erase the old binary data. A UV-transparent lid on the packaged EPROM chip allows this erasure to occur. Following erasure, the new binary data is written to the EPROM by deactivating the chip select line in order to switch the EPROM data outputs to inputs. The EPROM address inputs are then set to a starting value, the desired data is connected to the data inputs and the data is written into the data storage register identified by the address inputs. The address inputs are then incremented and the cycle is repeated for each data storage register in the EPROM array.
In an EPROM read operation, the binary data stored in the data storage register identified at the address inputs is connected to the EPROM's data output buffers. If the EPROM chip select signal is activated, then the binary data from the selected storage register is provided to the databus.
FIG. 1A shows a conventional EPROM cell 10. EPROM cell 10 includes a buried N+ source region 12 and a buried N+ drain region 14 formed in a P-type silicon substrate 16 and separated by a substrate channel region 18. Overlying channel region 18 is a layer of insulating material 20, typically silicon dioxide. A polysilicon (poly 1) floating gate 22 is formed on the insulating material 20. Overlying floating gate 22 is a second layer 24 of insulating material, usually a composite layer of oxide-nitride-oxide (ONO). A polysilicon (poly 2) control gate 26 is formed on the ONO layer 24.
A plan view of this so-called "stacked gate" (or "stacked etch") EPROM cell 10 is shown in FIG. 1B. The structure of the standard "T-shaped" cell 10 shown in FIG. 1B derives its "stacked-gate" designation because of the self-aligned etching process which utilizes the vertical alignment of the poly 2 control gate 26 with the poly 1 floating gate 22 to complete the definition of the floating gate 22.
The processing sequence for defining the poly 1 floating gate 22 and the poly 2 control gate line 26 of the stacked gate cell 10 is as follows. Referring to FIG. 1A, first, a layer of polysilicon (poly 1) is formed on the silicon dioxide layer 20. The poly 1 layer and is then masked and etched to form poly 1 strips. The edges of the poly 1 strips are then utilized in a self-aligned arsenic implant step to formed the buried N+ source and drain regions 12 and 14, respectively. Next, an oxide-nitride-oxide (ONO) layer 24 is formed over the entire structure. This is followed by formation of a second polysilicon layer (poly 2) which is masked and etched to form the control gate line 26. The resulting poly 2 control gate line 26 is then used as a self-aligned mask to etch the interpoly ONO 24 and the underlying poly 1 floating gate 22 to define the final structure of the stacked gate cell 10 shown in FIG. 1A.
Traditionally, reductions in EPROM memory density have been accomplished by reducing the dimensions of the cell features produced by the photolithographic and etching procedures utilized in fabricating standard T-shaped EPROM cells. The shrinking cell geometries resulting from these process developments have led to corresponding requirements for new isolation schemes in order to accommodate the minimum cell pitch and to develop the sub-micron contacts which must be formed utilizing non-standard techniques.
For example, Hisamune et al, "A 3.6 nm.sup.2 Memory Cell Structure for 16 mb EPROMs, IEDM 1989, pg. 583, disclose a process for minimizing EPROM cell pitch utilizing trench isolation of the bit lines and tungsten plugs for bit line contacts. Bergemont et al, "A High Performance CMOS Process for Sub-micron 16 mv EPROM", IEDM 1989, page 591, also disclosed techniques for reducing the size of the standard T-shaped EPROM cell.
One way to avoid the special processing requirements associated with the fabrication of high density T-shaped EPROM cell arrays is to use a different type of cell which does not require the use of field oxide isolation and contacts in the array.
For example, U.S. patent application Ser. No. 539,657, filed by Boaz Eitan on Jun. 13, 1990 for EPROM VIRTUAL GROUND ARRAY, which application is assigned to Wafer Scale Integration, Inc., teaches a new contactless EPROM cell array and its associated process flow. The contactless concept disclosed in the Eitan application is very attractive because it allows high density EPROMs to be fabricated without using aggressive technologies and design rules. The basic idea of the Eitan disclosure is the use of a "cross-point" EPROM cell, i.e. a cell which is defined by the crossing of perpendicular poly 1 and poly 2 lines in a virtual ground array. In order to avoid drain turn on, i.e. leaky non-selected cells on the same bit line during programming, and true virtual source decoding, metal contacts silicon every two bit lines and the non-contacted bit lines are connected to the Vss or Vcc lines via an access transistor. FIGS. 2 and 3 show an array layout and the equivalent circuit, respectively, for the Eitan cell.
However, there are several problems and disadvantages associated with the Eitan process flow. First, five layers of processing are required over the poly 1 layer: oxide/nitride/oxide/poly cap/nitride. The poly 1 and the five overlying layers are defined twice, once at poly 1 mask and once at poly 1 island mask. These two etching steps are very critical because they define, respectively, the length and width of the EPROM cell. Etching more layers in this way presents more difficulties in critical dimension control. Also, failing to remove any one of the five layers presents the risk of poly 1 stringers along the edges of the field oxide. These edges are located in the neighborhood of the access transistors, as well throughout the array.
Because the poly 2 in the Eitan structure is not self-aligned with the poly 1, a special "array field implant" is required in order to avoid leakages between adjacent bit lines. These leakages occur when poly 2 is misaligned with poly 1. The poly 2 controls one part of the silicon and leads to a parasitic poly 2 transistor between adjacent bit lines. For this reason, a high threshold voltage is required to avoid the turn on of this parasitic poly 2 transistor. This is done using an array boron field implant.
In addition to the implant, the Eitan process calls for an "isolation oxide" to move the field threshold to a sufficiently high voltage. This field implant leads to boron lateral diffusion into the channel of the cell, leading to channel width reduction, high bit line loading and reduction of the bit line to substrate breakdown voltage.
Additionally, the poly 2 etch is very critical in the Eitan process. The poly 2 etching terminates on a poly cap. In order to maintain the coupling ratio, it is necessary to stop the etch within a nominal poly cap thickness. This is difficult from the point of view of overetched latitude with a thin poly cap layer. Depending on the thickness of the isolation oxide, poly 1 to poly 2 misalignment will affect the parasitic capacitance of the word lines.
Furthermore, removing the top nitride before poly 2 deposit may affect the quality of the oxides all around the poly 1 floating gate. This could affect program disturb and data retention.